Part of the hierarchical development flow is about to get a lot simpler, thanks to a new standard being created by Accellera. What is less clear is how long will it take before users see any benefit.

In the realm of safety-critical electronic hardware, particularly those governed by DO-254 compliance directives, ensuring design integrity is paramount. One of the most insidious challenges designers ...

Metastability is bound to occur in VLSI designs during clock domain crossing. For a robust and reliable design, metastability needs to be mitigated. To understand how to resolve it and how to build a ...

An increasingly critical area of chip design is that of clock-domain crossings (CDCs). This goes not only for ASICs and systems-on-a-chip (SoCs), but also for FPGAs as well. All the problems designers ...

Here are some of the main reasons why metastability may occur in our designs and some of the ways in which we can mitigate its effects In my previous column, we introduced the concept of setup and ...